Santa Clara, CA · building in silicon

Hi, I’m
Shashank.

ASIC design engineer at NVIDIA working on ARM-based CPU RTL, power, and timing.

01 signal / architecture / curious

About
my work.

I’m a CPU design engineer at NVIDIA, working on RTL for ARM-based processors.

I have worked in CPU design, physical design, ASIC testing, EV charging, and network visualization.

EDUCATION
Georgia TechM.S. Electrical & Computer Engineering · 4.0 / 4.0
RV College of EngineeringB.E. Electronics & Communication · 9.52 / 10

Things I’ve
worked on.

Selected experience by role
and year.

2023 — now

NVIDIA · Santa Clara

ASIC Design Engineer

RTL design for ARM architecture-based processors. I work across out-of-order scheduler and execute pipeline blocks, shaping features with Verilog and improving power, timing, and architecture along the way.

RTLVerilogCPU designSynopsys Verdi
2022

Meta Platforms · Sunnyvale

Silicon Physical Design Intern

Optimized cell placement from RTL hints and integrated a Python-based RTL generation flow for ML accelerators, seeing 1–5% improvement in average power.

Physical designPythonML accelerators
2022

NVIDIA · Remote

ASIC Design Intern · CPU

Implemented decode-stage RTL features for multithreading and instruction decode, then automated global flows and internal reporting with Perl, Makepp, Bash, and REST APIs.

CPUAutomationBash
2021

Analog Devices · Bengaluru

Engineering Intern

Built a digital fault-injection workflow for an ASIC battery-management system. Designed six SPI tests and reached 96% coverage.

ASICDFI96% coverage
2017 — 2021

Team Chimera · Formula SAE

Safety Circuits Engineer

Designed, prototyped, and tested component-level safety circuits for an electric race car, including the brake system plausibility device and the insulation monitoring device. Built the dashboard driver information system on a PHYTEC ARM single-board Linux computer, bridging the Kelly motor controller and the LinearTech BMS over CAN. Electrical Systems Officer at Formula Bharat 2020.

Safety circuitsCANEmbedded LinuxFormula Bharat

Selected
projects.

Work across hardware,
software, and systems.

01 / 112024
NIR
SIGHTED

Architecture · low power

Streaming architecture for always-on vision

A programmable streaming architecture for low-energy, human-centric vision applications. Published in ACM Transactions on Embedded Computing Systems.

Read the paper
02 / 112024
INTRA-BODY
POWER

Wearables · energy transfer

Health wearables powered through the body

Bootstrapping battery-free health wearables using power transferred across the body. Presented at IEEE Body Sensor Networks 2024.

Read the paper
03 / 112022—23
SMART
CHARGING

Embedded · cloud · mobile

Smart Charging Systems for EV

An embedded system, cloud server, and mobile app for Level 1 and 2 EV charging. The algorithm optimizes for cost, environment, and time. Patent pending.

Read the paper
04 / 112022
GARNET
VISUALIZER

Python · GEM5

On-chip network traffic visualizer

A Python tool for finding bottlenecks and link usage in Garnet2.0. Presented at the GEM5 Workshop 2022.

05 / 112021
A*
ADAPTIVE
TESTING

Python · iVerilog

Test vector reordering for an FSM

An adaptive low-power test pattern generator using A* search. Achieved 94% fault coverage on the test circuit.

See the publication
06 / 112021
CELL
BALANCING

MATLAB · Simulink

Cell balancing for lithium-ion packs

Designed and simulated passive and active cell balancing techniques for lithium-ion batteries, comparing their performance.

07 / 112019
DRIVER
ALERTNESS

Java · Android

Driver alertness system

Detects a distracted driver from the road. Built at the Smart India Hackathon 2019 finals, where the idea was picked as one of the top four.

See the code
08 / 11 · Python

PyPODEM

Test generation with the PODEM algorithm, paired with a fault simulator that checks the patterns it produces.

See the code
09 / 11 · Python

PyDeductiveSim

A deductive fault simulator that propagates fault lists through a circuit to measure coverage.

See the code
10 / 11 · C++

Out-of-order
pipelined processor

Five-stage simulation with reorder buffers, forwarding, and Gshare branch prediction.

11 / 11 · FPGA

Real-time image
filtering

Efficient matrix operations and data acquisition for medical imaging on FPGA.

Read the paper

Always
learning.

C / C++PythonVerilogSystemVerilogJavascriptComputer ArchitectureCadencePower + TimingARMDigital VLSIAndroidPhysical Design

Wins and
scores.

Competitions, papers,
and exams.

  • 2022
    IEEE RoboTech HackQualcomm second place and Best Electrical Project · IEEE Georgia Tech
  • 2020
    Best PaperOptical fibre communication using an open-source expEyes-17 device · International Conference on Multidisciplinary Technologies and Challenges in Industry 4.0
  • 2020
    Second place, e-Yantra RoboticsMaze-solving robot challenge at IIT Bombay, from over 1000 teams
  • 2019
    First place, Infineon HackathonOptimised an encryption system on an embedded target, in a team of four
  • 2019
    Top four, Smart India HackathonDriver assistance system for identifying a distracted driver · Government of India
GATE ECEAIR 1243Feb 2021
GRE326Aug 2020
IELTS8.0Sep 2020
COMEDKRank 16May 2017
KCETRank 280Karnataka common entrance test

contact

Get in
touch.

For questions about my work or potential opportunities, email me directly.